1. Field of the Invention
The present invention relates to providing cache coherency in a computer system having a central processing unit (CPU) and other devices that monitor the system bus by "snooping". More specifically, coherency is maintained between asynchronous buses by altering the criteria used to compare and identify the memory address of data owned by a first device and requested by another device.
2. Description of Related Art
A problem exists with conventional multi-cache systems having asynchronous buses and a snooping protocol in that a time period exists when the address of data being written to a cache is invalid. If a snoop comparison occurs during this time period (due to the asynchrony between the update and the snoop comparison) an erroneous response may cause performance degradation or incorrect data in the system. This erroneous response may include a false snoop hit, or an actual snoop hit that was not identified. More particularly, due to the asynchronous nature of input/output (I/O) devices writing to, or reading from, a cache memory included in an input/output channel controller (IOCC), a period of time exists when the I/O device is ending its interaction with one memory sector and beginning to interact with another memory sector. Thus, the sector address used for a snoop comparison is in a state of transition such that if a snoop of the system bus occurs during the address transition time period, then an erroneous snoop hit or failure to detect a snoop hit may occur.
A conventional solution for maintaining cache coherency is described by U.S. Pat. No. 5,119,485 which involves coupling an encoded control signal from an alternate busmaster to a bus interface control circuit to selectively enable data bus snooping. U.S. Pat. No. 5,072,369 discusses mapping addresses across different buses to ensure coherency. That is, an interface circuit maps selected bus addresses to corresponding addresses on another bus such that when a busmaster on a first bus attempts to read or write a bus interface circuit responds by accessing a corresponding address in the memory of the second bus.
Another method of cache coherency is described by U.S. Pat. No. 5,025,365 which has distributed directories which allow updates of each cache memory at different time periods. This causes directory inconsistencies to occur during the period between updates. A system bus protocol is arranged to provide a periodic correct operation to maintain,data coherency by updating the distributed directories. U.S. Pat. No. 5,193,170 includes a CPU, RAM and ROM. During a ROM mapped to RAM mode a snoop cycle is implemented to detect any CPU write operations and, if detected, a cache invalidation signal is sent to the CPU. U.S. Pat. No. 4,945,486 includes a series of processors connected through a shared data bus with each processor generating a synchronization request signal. A synchronization controller broadcasts the processor status on a synchronization bus, thereby enabling snooping of the bus to monitor communications.
It can be seen that conventional systems use various techniques, such as mapping, distributed directories, synchronization processor, enabling bits, and the like to maintain cache coherency. These conventional systems solve cache coherency problems in a synchronous system, but do not address the additional problems encountered when at least two buses in the system are asynchronous. Therefore, it can be seen that a system which redefines existing parameters in a system to provide cache coherency between asynchronous buses without the need for additional complex logic would be extremely advantageous.